1. Field of the Invention
The present invention relates to a shared cache memory, and more particularly to a multiprocessor system and to a method of controlling hit determination of a shared cache memory in a multiprocessor system that includes a plurality of processors that share a multiple-way (n-way) set-associative cache memory that includes a directory and a data array, the multiprocessor system being partitioned such that the plurality of processors each operate as independent systems.
2. Description of the Related Art
In a multiprocessor system in which a plurality of processors share a cache, and moreover, in a multiprocessor system that has been partitioned to allow the plurality of systems to operate independently, each partition operates as an independent system (OS), and processors may therefore in some cases use the same address to refer to different memory sites.
Thus, when a different partition has registered a different memory block in the cache by the same address, a partition that refers to the cache at the same address may cause a conflicting cache hit.
An example of such a conflicting cache hit will be explained hereinbelow with reference to FIGS. 1A, 1B, 1C, and 1D. It is first assumed that the system is partitioned such that partition K1 is processor 0 and partition K2 is processor 1. Processor 1 (partition K2) sequentially supplies as output addresses X, Y, P, and Q in memory blocks A, B, C, and D, following which processor 0 (partition K1) sequentially supplies as output addresses R, Y, P in memory blocks E, F, and G. It is further assumed that each of the above-described blocks A-G are blocks in the same set i and that the cache memory is in the initial state.
When processor 1 (partition K2) supplies addresses X, Y, P, and Q in blocks A, B, C, and D, copies of blocks A, B, C, and D are stored in ways 0, 1, 2, and 3 of set i of data array 214 as shown in FIG. 1A.
The subsequent output of address R in block E by processor 0 (partition K1) results in a miss, and the copy of block A that was stored in way 0 is replaced by the copy of block E.
The subsequent sequential output from processor 0 of addresses Y and P in blocks F and G (the same addresses as blocks B and C) results in a cache hit at ways 1 and 2 that were registered by partition K2, as shown in FIGS. 1C and 1D, resulting in a conflicting cache hit.
As one example for preventing such a conflicting cache hit, Japanese Patent laid-open No. 2001-282617 discloses a case in which bits for storing partition numbers are extended on all cache tags, and a comparison circuit, when carrying out hit determination, determines partitions that are registered in the cache. As a result, cache hits are guaranteed not to occur in cache blocks that are registered in other partitions, and conflicting cache hits are therefore prevented.
However, a method in which bits are added to a cache tag and shared cache areas are allocated to each partition such as the aforementioned Japanese Patent No. 2001-282617 also entails an increase in the hardware construction. The above-described method is therefore problematic because it does not allow miniaturization of the shared cache, miniaturization of an on-chip multiprocessor system having a limited chip area, or a reduction in costs.